Why doesn't Systemverilog need a 'main' function like Java?

In reply to dave_59:

Hi Dave,

A further query about the difference of interface between java with SV.

I know that ‘interface’ along with ‘implements’ is one of the key concepts of OOP in Java.
It helps to achieve the abstraction and encapsulation of OOP.

However, it looks like ‘interface’ in SV is commonly used to declare the ports of a hardware.
I think the ‘interface class’ in SV is the one equal to ‘interface’ in Java. However, it seems to be not much used (as far as I know).

Above are just my immature thoughts.

  • Could you explain that in your vision?
  • Should we use more more OOP, more design pattern just like software in our tb design to achieve the performance goals such as abstraction, encapsulation reusability, extensibility etc?
  • I know UVM is leveraging many design patterns which makes UVM itself more OOP. However, even we used UVM to build up the project testbench, when there is a new project, copy/paste and modify the ‘class’ directly is more common than leverage OOP features such as override, inheritance, polymorphism.

Regards
Shawn