Why does the UVM factory use a proxy when we register a class in the factory?

In reply to Verif Engg:

A proxy is a way of representing the class type as another object. You can’t pass types around dynamically like you can pass a handle to an object. Think of the proxy class handle as an encoded value that represent a type you want to construct.

Please see my course on SystemVerilog OOP, especially the 3rd session.

Also see this paper: Using parameterized classes & factories: Object-oriented verification