Why does input logic is not a var, while output logic is a var?

SystemVerilog
1

Hi,
In the below code:

module my_top(
	             input logic my_valid,    //not a var fails 
                     output logic sig             //is a var passes  
	           );

endmodule
//=================
interface my_if (ref logic sig,
                             ref logic my_valid);
endinterface : my_if
//=================

module my_tb();
	
	my_top my_top();
	bind my_top my_if my_if_bind(.sig(sig), .my_valid(my_valid));

	initial begin
       #50;
	   $finish;
	end
endmodule

I understand that A ref port is always a variable.
Why does input logic is not a var, while output logic is a var?

Thanks,
Tsach

2

Verilog, a hardware description language, caters to hardware engineers who are lazy when it comes to writing code. It offers numerous implicit default settings for ports. The rules outlined in section 23.2.2.3 Rules for determining port kind, data type, and direction specify that if the kind (variable or net) is omitted, input and inout ports are implicitly defined as nets. However, for output ports, their kind defaults to a variable if a data type is present.

These differences in defaults were established because it’s uncommon to want an input port to be a variable. However, this does introduce additional complexity to learning the language.