Why does display function change the value?

SystemVerilog
1

Hi, I met a weird question.

I used 12 bits interface connect to 8 bits output of DUT, and the 8 bits initial to zero.
So it does make sense that the dut_if.test_signal value is X00 (hex).

However, when I use display function to show the data, display function change the variable value ? and the dut_if.test_signal value is changed to 000 (hex).

The residual 4 bits is modified to 0!

Personally, the display function shouldn’t modify the variable value, But it does.

I did a simple example as below, and compile it with xrun (Cadence Tool),

By the way, when I used the vcs (Synopsys) to compile it, the residual 4 bits is padding to zero in the beginning even if no display function.

interface dut_io;
     bit clk;
     logic [11:0] test_signal;
endinterface: dut_io


module dut(clk, test_signal);
     input clk;
     output reg[7:0] test_signal;
     
     initial begin: set_data
         test_signal = '0;
     end   
endmodule: dut

module top;
    dut_io dut_if();
    dut dut1(.clk(dut_if.clk), .test_signal(dut_if.test_signal));

    initial begin: clock
        forever begin
           #10;
           dut_if.clk = ~dut_if.clk;
        end
    end: clock
    

    initial begin: fsdb
        $fsdbDumpfile("unknown.fsdb");
        $fsdbDumpvars(0, top, "+all");
    end: fsdb 


    initial begin: testblock
        #200;
       
       // if use display, the  dut_if.test_signal change from x00 to 000 (xrun)
       // $display("signal: %x", dut_if.test_signal);
       
        $finish; 
    end: testblock
endmodule: top
2

I’m unable to reproduce your behavior with all 4 tools on EDAPlayground. You should doublecheck that you entered the code correctly as yours has mismatched begin/end statements.

The correct behavior is padding the test_signal with 0s. This is because your module port connection is a variable inside the dut module and it is being connected to a variable in the top module. That gets treated as an implicit continuous assignment. The fact that dut_io is an interface is irrelevant here.

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