Why does an uninitialized fixed array get initialized to 0 or 1 using for loop

SystemVerilog
,
2

In reply to yr:


one is a 1 bit array. What do you expect? it stores lsb.
// 000 001 010 011 100 101 

what you want is below i guess?

module tb;
  bit [2:0] one[6];
int total;
initial begin
foreach(one[i])
one[i] = i;
 
$display("%p",one);
end
endmodule