Which registers sequences/tests should we run for verifying completely registers functionality?

UVM
, ,
8

In reply to Michael54:

Thank you Rsignori92 and chr_sue!
What about accessing undefined addresses in the address space?
Of course we won’t have a register defined for this in the RAL… Should we test it as well. How can we issue a RD/WR to such address?

In the adapter you can do things like this

virtual function void bus2reg( uvm_sequence_item bus_item, 
                                 ref uvm_reg_bus_op rw);
    my_transaction tr;

    ok = $cast(tr, bus_item);
    assert (ok) else       `uvm_fatal("ADAPTER", "Not a legal transaction!")

    if (tr.addr >= LEGAL_ADDR_REGION) begin
      rw.kind = (tr.kind == my_transaction::BUS_READ) ? UVM_READ : UVM_WRITE;
.....
endfunction