In reply to logie:
This is used as a workaround for the fact that earlier versions of SystemVerilog did not support non-blocking assignments to class variables. (the code that is inside the …)
And there is also a comment saying you would need to define this if the UVM library was `included in a program block instead of a module. This is also not needed. Only the earliest version of SV had a restriction about NBA’s in program blocks.