In reply to ben@SystemVerilog.us:
Actually, I have written simple enough constraints for APB protocol. And I have created a reference model to mimick DUT.
So my assertions are just to compare reference model output with DUT output on every active clock edge.
In this scenario, can you give me any approaches for Inconclusive Assertions? Also, it would be helpful, if you can give me any paper/article related to Assertion Based Formal Verification, as I am not able to find much on this topic.