What should be my approach verifying time constraints in the signals of a interface

SystemVerilog
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2

In reply to aarelovich:

You can use assertions for this, I can give you a small example:


  property p_check_hole_time;
   time t1, t2;
   @(posedge clk) (1, t1 = $time) |-> @(posedge clk) (1, t2 = $time) ##0 ((t1 - t2) == 2ns, pass_msg);

  endproperty

Here if you can see I have taken 2 variables t1, t2 inside a assertion and am using to store the time. You can it in a same way in writing a assertion.
Note: this is just a skeleton and its not compile free.