In reply to edcarstens:
One thing to remember is that parentheses ‘()’ only affect precedence of operator ordering. The parentheses have no effect on the original example because unary ~ has higher precedence than binary + anyways. Verilog bit-length rules say that operands of context determined expressions (+ and = are both context determined expressions) are extended to match the size of the largest operand, and the LHS of an assignment is an operand as well.
If you write the expression as a concatenation:
assign temp_n = {~aaa} + 3'd1;
This works as you originally expected because because all operands of a concatenation are self-determined - the bit-length of ~aaa is solely determined by the bit-length of aaa.
See 11.6.1 Rules for expression bit lengths in the IEEE 1800-2012 LRM