What is the exact difference between static tasks/functions and automatic tasks/functions ? please explain with a clear example

SystemVerilog
6

In reply to Hardik Trivedi:

Hi Hardik,

  Dave's explanation should clear your confusion between automatic and static.

For calculating the factorial, the function should be automatic so that there will be multiple memory allocations for the variable “factorial” which is a property of recursive function. If the function is static, then memory for the variable ‘factorial’ will be only once and finally factorial value is becoming ‘1’ in the recursive calls.

Consider the following example also for understanding the difference between static and automatic.


module test();

task add(int a, int b);
	#2;
	$display("the sum is %0d", a+b);
endtask

initial
	fork
		begin
			add(2,3);
		end
		begin
			#1;
			add(3,4);
		end
	join
endmodule

In the above example, the task add is static. So, memory for the variables a & b will be allocated only once. Hence, output for the program will be as follows (which will be definitely different from your prediction).

the sum is 7
the sum is 7.

make the task as automatic and see the difference.

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