The lifetime of a function or task is a concept that I’ve only seen in Verilog. Verilog started out with having only static lifetimes of functions or tasks, meaning that there was no call stack for arguments or variables local to the routines. This meant you could not have recursive or re-entrant routines, unlike most other modern programming languages. The thinking was synthesis could not create stacks of memory dynamically when called. Verilog 2001 added the ‘automatic’ lifetime qualifier to give routines the normal behavior of most programming languages. SystemVerilog added a lifetime qualifier for modules and interfaces so that all routines defined in that module would be considered automatic by default so you didn’t have to add the automatic keyword after each function or task declaration. SV also added the ‘static’ lifetime qualifier so that if for some stupid reason you declared a module as ‘automatic’ but still needed a particular function inside that module to have the original Verilog behavior. The
static or
automatic lifetime qualifier appears to the right of the
function or
task keyword.
Note that the lifetime of class methods are always automatic, you cannot even declare them with a static lifetime. This is not to be confused with a static class qualifier, where the static keyword appears to the left of the function or task. This means it is a method of the class type, not of a class instance or object.
Look at the tryfact example in 13.4.2 Static and automatic functions and see what happens if you don’t make the factorial function automatic.