What is the difference between packed structure and union in system verilog?

Understanding LRM idioms can be a bit difficult if you’ve just started reading it. Main difference between structure and union is that,

  • Structure consists of different fields which can be accessed by their names. And storage is allocated for each of these fields.
  • Whereas in Union there’s only single storage which is maximum of storage that a field can require to store data. And this common area can be accessed as any of the field name, if done carefully.

Concept of packed structure/ packed union deals with efficient memory allocation and does not change inherent behavior of struct/union data types.

You’ll also find lot of details on structure and union if you remove search word “SystemVerilog” from it! This is same across all different language.