In reply to Mukund Sojitra:
What is “not” property operator in System verilog Assertion?
please explain with example.
The answer is in 1800.
1800’2012
16.12.2 Negation property
A property is a negation if it has the form not property_expr. For each evaluation attempt of the property, there is an evaluation attempt of property_expr. The keyword not states that the evaluation of the property returns the opposite of the evaluation of the underlying property_expr. Thus, if property_expr evaluates to true, then not property_expr evaluates to false; and if property_expr evaluates to false, then not property_expr evaluates to true.
The not operator switches the strength of a property. In particular, one should be careful when negating a sequence. For example, consider the following assertion:
a1: assert property (@clk not a ##1 b);
Since the sequential property a ##1 b is used in an assertion, it is weak. This means that if clk stops ticking and a holds at the last tick of clk, the weak sequential property a ##1 b will also hold beginning at that tick, and so the assertion a1 will fail. In this case it is more reasonable to use:
a2: assert property (@clk not strong(a ##1 b));
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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