Using events in SystemVerilog requires careful knowledge of simulation execution semantics. I usually recommend avoiding them if possible.
An event trigger ->e is an instantaneous event. The event control @e has to execute and block the current process before the trigger occurs in another process, and the block process resumes. Many times there are race conditions between the two processes and the trigger executes before the event control, and the event is missed, and the event control has to wait for another trigger.
The wait(e.triggered) statement says wait for the condition that event e has been triggered in the current time slot. Now you no longer have to worry which came first, the trigger or the wait statement. But you still have to execute the wait statement in the current time slot to catch the event.
Better options include using a mailbox or semaphore; and the UVM has other options as well, depending on what you are trying to accomplish.