In reply to mbhat:
Yes, I have implemented interface using clocking block and modport, and skew is included, the main problem for me I think is the correct generation of all control signals and timing with respect to clock cycles. I am doing it for the first time so I am still struggling here.
There are just five signals here: valid, start, length that indicates the packet length, and ready, It must be easy, but for me it is not. QAQ(crying)
Thanks anyway.