What am I doing wrong about the replication operator?

SystemVerilog
,
4

In reply to jh_veryveri:

I’m sure there are ways of doing this more efficiently, from what I understood from your post this might work


// Code your testbench here
// or browse Examples
`define USER_WIDTH 4
class wrapper;
  
  function bit compare(logic [`USER_WIDTH - 1:0] A, logic [`USER_WIDTH-1:0] B);
    
    
    int B_valid_width = (B != 0) ? $clog2(B) : 1;
    int A_valid_width = (A != 0) ? $clog2(A) : 1;
    
    bit [`USER_WIDTH - 1:0] mask = {`USER_WIDTH{1'b1}};
  
    $display("mask before = %b", mask);
    $display("A = %b A_valid_width = %0d", A, A_valid_width);
    $display("B = %b B_valid_width = %0d", B, B_valid_width);
    
    
    if (A === B) begin
        return 1'b1;
    end 
    else begin
      if (A > B) begin
        mask >>= B_valid_width;
        $display("A > B mask after = %b", mask);
        return ((A & mask) == B);
      end
      else begin
        mask >>= A_valid_width;
        $display("A < B mask after = %b", mask);
        return (A == (B & mask));
      end
    end
    
    return 1'b0;
  endfunction

endclass

module test();
  wrapper m_wrapper;
  logic [`USER_WIDTH-1:0] X;
  logic [`USER_WIDTH-1:0] Y;
  bit result;
  initial begin
    X = 'b0011;
    Y = 'b0100;
    m_wrapper = new();
    
    result = m_wrapper.compare(X, Y);
    $display("X = %b Y = %b result = %0b", X , Y, result);
    
    Y = 'b0111;
    result = m_wrapper.compare(X, Y);
    $display("X = %b Y = %b result = %0b", X , Y, result);

  end
endmodule

This outputs


# KERNEL: mask before = 1111
# KERNEL: A = 0011 A_valid_width = 2
# KERNEL: B = 0100 B_valid_width = 2
# KERNEL: A < B mask after = 0011
# KERNEL: X = 0011 Y = 0100 result = 0
# KERNEL: mask before = 1111
# KERNEL: A = 0011 A_valid_width = 2
# KERNEL: B = 0111 B_valid_width = 3
# KERNEL: A < B mask after = 0011
# KERNEL: X = 0011 Y = 0111 result = 1

HTH,
-R