What am I doing wrong about the replication operator?

SystemVerilog
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2

In reply to jh_veryveri:

First you should explain what not working means and what kind of error you are getting
I assume your problem is A_valid_width as stated in the LRM is should be a constant expression or a parameter, which is different from a const variable, you could try doing a masking, I think there are plenty of examples in this forum.

11.4.12.1 Replication operator A replication operator (also called a multiple concatenation) is expressed by a concatenation preceded by a non-negative, non-x, and non-z constant expre

HTH,

-R