Weighted constraint

SystemVerilog
1

hello,

i am using weighted constraint for generation arith only for two times.
but as per expectation it is not coming sometimes 3 or 5 or zero times arith value is comming
below is my code.

class alu_trans_c;

  typedef enum {LOGIC,ARITH, SHIFT} operation;
  rand logic [3:0] alu_sel_in;
 rand operation rand_oper;

// Apply following constraints
  constraint t1 {rand_oper dist {ARITH :=2,LOGIC:=3,SHIFT:=5};
                 rand_oper==LOGIC ->alu_sel_in inside {[0:5]};
                 rand_oper==ARITH ->alu_sel_in inside {[6:9]};                   rand_oper==SHIFT ->alu_sel_in inside {[10:15]};}
  
 function void post_randomize();
   $display("random values for %d are : %0d",rand_oper,alu_sel_in);
 endfunction
 endclass

 alu_trans_c al;
 module test_random;
 initial
begin
 al=new();

 repeat(10)
   begin
 assert(al. randomize( ));

 end
end
   endmodule
2

Please format your code making your code easier for others to read. I have done that for you.

3

Can you please try this.

constraint t1 {rand_oper dist {LOGIC:= 3, ARITH := 2, SHIFT:= 5};
rand_oper==LOGIC ->alu_sel_in inside {[0:5]};
rand_oper==ARITH ->alu_sel_in inside {[6:9]};
rand_oper==SHIFT ->alu_sel_in inside {[10:15]};}