Web Seminar Notification: One Stop Verification IP with Mentor Graphics Memory Library

Are you a Verification Engineer or Manager interested in Verification IP?

One Stop Verification IP Memory Library


Fast and Accurate memory models are needed to verify the memory controllers used to communicate with external memories used by today's SoCs. Mentor's memory library models over 1600 DRAM and flash memory devices, including leading edge protocols such as Hyperbus. The memory library also includes controller VIP for all protocols that can be used to verify memories or PHYs. Together with the Questa Verification IP (QVIP) Protocol Library, the memory library provides a complete standards based SystemVerilog/UVM solution to all your VIP needs.

What You Will Learn:

  • Rapidly generate memory models and quickly integrate them into your testbench using Mentor's memory configurator software
  • Verify your memory controllers with assertions, coverage, and transaction level debug
  • Easily switch between primary and second source memory models using Mentor's unique on-the-fly reconfiguration

Now available to view or download.