Are you a Verification Engineer or Manager interested in Verification IP? One Stop Verification IP Memory LibraryOverview: Fast and Accurate memory models are needed to verify the memory controllers used to communicate with external memories used by today's SoCs. Mentor's memory library models over 1600 DRAM and flash memory devices, including leading edge protocols such as Hyperbus. The memory library also includes controller VIP for all protocols that can be used to verify memories or PHYs. Together with the Questa Verification IP (QVIP) Protocol Library, the memory library provides a complete standards based SystemVerilog/UVM solution to all your VIP needs. What You Will Learn:
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