We have 32 bit address in which 1 bit is one . write a condition to get it in descending order?

SystemVerilog
1

For this i having the below code.

class packet;
  rand bit [31:0] address;
  rand int arr=0;
  constraint c1 { $countones(address) ==1;}
  
  function void post_randomize();
   for (int i=32; i>arr;i--)
   address[i] =1;      
  endfunction                
endclass

module abc();
  packet pkt;
  initial begin
    pkt=new();
    //repeat(5) begin
    pkt.randomize();
    $displayb(pkt.address);
    //end
  end
endmodule

but my expectation when i call multiple times randomization for the first 32nd bit should be 1 and for second time randomize() call 31st bit should be 1 and so on like that.
But i am getting the solution as below 11111111111111111111 (32 times 1).

Can any one pls help me with this.

Thanks & Regards,
Manikanta K.

2

This output is possible only when ‘arr’ is randomized to a negative value
Also note that the for loop won’t execute if the random value of ‘arr’ is greater than or equal to 32.
Here is one possible solution

class packet;
  rand bit [31:0] address;
  bit [4:0] arr; // Iterates from 0 to 31 i.e Index values of address
  constraint c1 { address == ( {1'b1,31'b0} >> arr ) ;}
  
  function void post_randomize();
   arr++;   
  endfunction                
endclass

module abc();
  packet pkt;
  initial begin
    pkt=new();
    repeat(34) begin
      if( pkt.randomize() )
       $displayb(pkt.address);
    end
  end
endmodule