I know normally virtual interface is the right way to do such tasks.
In my case, there’s no potential needs for re-use and all I need is to probe 1 bit signal which is inside the DUT. Therefore I try to avoid making the TB bulky, just added a simple “if” statement to the main_phase in my test, which seems to be working well.
I do remember I used to hit some compile errors years ago while doing similar things.
I’m wondering if this is some new change in the UVM, SV or maybe the simulator?
Since you mentioned reuse is not a concern, such access is indeed allowed - as long as the test/class is outside a package.