In reply to mseyunni:
I talked with my co-authors about some suggestions for your requirements, which are:
I have a requirement where I would like to end the simulation whenever I have seen all the responses out of DUT or the timeout whichever occurs earlier. Also the request and response interfaces being different, how can we update / modify the above code to suit my requirements.
They suggested something that I should have done initially, is to use SVA with uvm_error or uvm_fatal.
The assertions can be put in the DUT, or in interfaces, or in checkers bound to DUT or interfaces, or in the testbench module.
The use of assertions is much better than a plain counter as it would not add to synthesis area (the checker version would not add either if you use the counter there)
Below is an example for the application of assertions with uvm_error and uvm_fatal.
import uvm_pkg::*; `include "uvm_macros.svh"
module dut #(parameter MAX_DEL = 200)
(input logic clk, rst_n, output logic activity);
logic [7:0] count;
always_ff @(posedge clk) begin : act
if (!rst_n) begin : reset
count <= 0;
activity <= 1'b0;
end : reset
else begin : work
if (count < MAX_DEL) begin : b1
activity <= 0;
count++;
end : b1
else begin : b2
count <= 0;
activity <= 1;
end : b2
end : work
end : act
endmodule : dut
module tb;
parameter MAX_IDLE = 30;
bit clk, rst_n, activity;
dut dut (.*);
always #10 clk <= ~clk;
default clocking @(posedge clk);
endclocking
initial begin : test
##10;
rst_n <= 1'b1;
##10000 $finish (2);
end : test
a_wake_up_after_rst : assert property (p_wake_up)
`uvm_error("ID", "did not wake up"; // removed the "else"
a_dont_be_lazy : assert property (p_dont_be_lazy)
`uvm_fatal("ID", "did not wake up_other assertion");
property p_wake_up;
$rose (rst_n) |-> ##[1:MAX_IDLE] !$stable(activity);
endproperty : p_wake_up
property p_dont_be_lazy;
!$stable (activity) |-> ##[1:MAX_IDLE] !$stable(activity);
endproperty : p_dont_be_lazy
endmodule : tb