Watchdog Timer

UVM
,
2

In reply to mseyunni:

could be as simple as a down counter.

module counter_max #(MAX_COUNT=99999)( // parameter port list 
            output logic timeout, 
            input logic clk, rst_n,
            input bit activity) ;
    	int counter=MAX_COUNT;
 
        always @(posedge clk) begin : counter1
            if(!rst_n || activity) counter <= MAX_COUNT; 
            else counter <= counter - 1'b1;
            if(counter==0) timeout <= 1'b1; 
            else timeout <= 1'b0;
        end : counter1
	
    endmodule : counter_max