In reply to ben@SystemVerilog.us:
Hi Ben,
Thanks for persisting with my questions (hopefully this will be the last one). Though I understand the above code, apologies, I actually wanted this monitoring to be done somewhere (interface, a system monitor or in the test itself ) and use this as a way to stop the test/simulation in case there is a hang in the RTL. I see the above code could be used as the checker, but feeding this to test (which is what I was after) helps ending the test as well report it as a fatal / error with a message “Test ending due to timeout” etc.
Thanks,
Madhu