Warning: Non-existent associative array entry. Returning default value

SystemVerilog
,
4

In reply to ce_2015:

Actually, I try this and it works fine in local and even SystemVerilog Randomization - EDA Playground
maybe check your tool first. It’s valid syntax.


class txn;
  typedef enum bit [3:0] {A,B,C,D} sometype_t;   
  rand int array[sometype_t] = '{default:0, A:1, B:2, C:3, D:4};   
endclass

module automatic test;
  
  function void run;
    txn tmp = new();
    $display("template : %p", tmp); // '{array:'{A:1, B:2, C:3, D:4} }

    tmp.randomize();
    $display("template : %p", tmp); // '{array:'{A:727460974, B:-2124444300, C:-816347820, D:2075578760} }
  endfunction
  
  initial run();
  
endmodule