In reply to modymiller:
Again the test doeas not know anything about our timing and the clock cycles. How do you observe an internal signal depends on what you prefer. bind is one option, uvm_hdl_read another one and using a hierarchical path is an third one. As I said you can add this internal signal to your SV inteface and observing in the driver what happens there. If the condzion happens you can create your response and put it back to the sequence.