Waiting for Interrupt trigger

UVM
,
1

Hi Forum,
In my IP’s env I wait for an interrupt to occur ::

virtual task pre_main_phase( uvm_phase phase );
  phase.raise_objection( this );
    fork
       begin
          forever @(posedge tc_vif_intf.tc_intr )
            begin
             // ISR Sequence  to clear TC interrupt
            end
       end
       begin
           forever @(posedge tc_vif_intf.map_intr )
             begin
              // ISR Sequence to clear Map interrupt
             end
       end
    join_none  
          phase.drop_objection( this );
endtask
  1. Is the objection raise and drop of any significance here ? ( due to join_none ) .
    The actual interrupt occurs due to a sequence started in main_phase() of the test.
    In the waveform I notice that the interrupt does occur later on ( when sequence has started sending txns. via main_phase() of the test ).
    However @(posedge tc_vif_intf.tc_intr ) / @(posedge tc_vif_intf.map_intr ) doesn’t unblock.

When I move the above code to main_phase() of env the event is triggered and ISR sequence executes.

  1. I was wondering why the ISR sequence doesn’t execute in pre_main_phase ?
    My initial thought is when phasing moves to test’s main_phase() , the env’s ( and all other component’s ) pre_main_phase() is killed essentially meaning that there is no event waiting for the interrupt signal

  2. Where should I ideally write this piece of code ? I can’t write in base_test as the test isn’t being reused at Sub-system level ( hence I chose in IP’s env which would be reused ). Should I write it in run_phase() of env ? So that if the sequence from test generates interrupt in pre_main_phase / main_phase / post_main_phase my ISR sequence would always execute

Thanks

2

Hi,

Try to move your code to uvm_component callback function:

phase_started

Read about it in the description:
“Any threads spawned in this callback are not affected when the phase ends.”

Please update if it worked.

3

Thanks Michael for your inputs.

“Any threads spawned in this callback are not affected when the phase ends.”

The quote does answer a question that I always had ::
Why not simply write a code in a particular_phase instead of using phase_started / phase_ended.

Will surely try it and get back to you.

4

Not sure the answer is that simple…
There are many different considerations to things which we see as the final outcome.
UVM has it phases and sub-phases, and additionally the callback functions that we might need to add there some functionality.
Since many test’s components might have same sub-phases (in general it is not recommended to mix UVM run_phase with the run_phase sub-phases), it is a good idea to have a callback functions, that you know will be called at the start/end of phase.
Otherwise you will need to add logic to make all components to be synchronized at their start/end phases, it is not an easy task…