Wait_for_state() doesn't work as expected

UVM
1

I tried using wait_for_state() of uvm_phase class to wait for a specific UVM phase in a module. I referred to the following UVM 1.2 document site.
wait_for_state()

Here is the TB code.

`include "uvm_macros.svh"
module tb;
    import uvm_pkg::*;
        
    class my_test extends uvm_test;

        function new(string name, uvm_component parent);
            super.new(name, parent);
        endfunction

        `uvm_component_utils(my_test)

        virtual function void build_phase(uvm_phase phase);
            `uvm_info(this.get_type_name(), "Build Phase", UVM_MEDIUM)
        endfunction

        virtual task run_phase(uvm_phase phase);
            phase.raise_objection(this, "Starting Run Phase");
            `uvm_info(this.get_type_name(), "Run Phase", UVM_MEDIUM)
            #100ns;
            phase.drop_objection (this, "Ending Run Phase");
        endtask

    endclass

    initial
      run_test("my_test");

    initial begin
      uvm_pkg::uvm_run_phase::get().wait_for_state(uvm_pkg::UVM_PHASE_STARTED);
      `uvm_info("TB", "Waited for Run Phase Start", UVM_MEDIUM)
    end

endmodule;

But this doesn’t work. “Waited for Run Phase Start” is not printed in the log.

# UVM_INFO @ 0: reporter [RNTST] Running test my_test...
# UVM_INFO testbench.sv(17) @ 0: uvm_test_top [my_test] Build Phase# UVM_INFO testbench.sv(22) @ 0: uvm_test_top [my_test] Run Phase
# UVM_INFO /usr/share/questa/questasim/verilog_src/uvm-1.2/src/base/uvm_objection.svh(1270) @ 100: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
# UVM_INFO /usr/share/questa/questasim/verilog_src/uvm-1.2/src/base/uvm_report_server.svh(847) @ 100: reporter [UVM/REPORT/SERVER]

Why doesn’t this work? Any issues?
Here is EDA Playground link.