You have written two different typedefs. You need to have one typedef in a package, and import it into both scopes.
Please see SystemVerilog Coding Guidelines: Package import versus `include - Verification Horizons
You have written two different typedefs. You need to have one typedef in a package, and import it into both scopes.
Please see SystemVerilog Coding Guidelines: Package import versus `include - Verification Horizons