(vsim-3971) $cast to type

In reply to lalithjithan:

There is no cast needed. SystemVerilog differentiates between the simple cast (using ') and the dynamic casting (using $cast). For the details see chapter 6.24 in the LRM. The details cannot be explained in a few lines only.
What you are doing can be simply done using an assignment like

xtn.trans_type = vif.mmon_cb.HTRANS;