In reply to tfitz:
In reply to tfitz:
By the way, I’m glad you enjoyed the UVM Rapid Adoption article. ;-)
Ive ready quite a few of both of your papers, this is my current favorite.
I wish I had it when I started SystemVerilog/UVM years ago. It’s what I would hand to a beginner to help them focus on the meat of UVM. I don’t think there is a painless way to learn UVM/SystemVerilog, but it definitely would pave the road a bit. I think the division of labor description is a really key point, especially for someone like myself, who works on a small team that has to wear all the hats. I can at least try to step into the shoes of, say, the “sequence writer” and decide what is appropriate to provide a “test writer”. This is what pushes me to get the complexity out of the test, and into the sequence, since they are the portable workhorses of the environment. Anyway, thanks for taking the time to write. I’d stick it in the “read-this-first” part of your teaching methodology.