Virtual methods in system verilog

SystemVerilog
3

In reply to dave_59:

Thanks Dave . I am still confused.But why doesn’t it happen in below code.

typedef enum {IDLE, RUN, P0, P1} cmd_t;

///// Base Class Declaration
class Packet;
 
 /// Properties
 cmd_t cmd;
 int status;
 bit [7:0] data [0:255];
 
 /// Method
 function void SetStatus (input int y);
 status = y;
   $display("base");
 endfunction: SetStatus
 
endclass: Packet

///// Extended Class Declaration
class myPacket extends Packet;
 
 /// Added Properties
 bit errBit;
 
 /// Newly Added Method
 function bit ShowError();
   return(errBit);
 endfunction: ShowError
 
 /// Overriding Method
 function void SetStatus (input int y);
   status = y + 2;
   $display("child");
 endfunction: SetStatus
 
endclass: myPacket

module top;

 Packet pkt = new;
 myPacket m_pkt = new;
 
 task my_run (Packet PKT);

   PKT.SetStatus(2);
   $display("Status value is = %0d", PKT.status); 
   endtask: my_run
 
 initial begin
   my_run(pkt);
   my_run(m_pkt);
 end
 
endmodule: top

and this is my output
base
Status value is = 2
base
Status value is = 2