You seem to be confusing Verilog module names with class handles. The way the uvm_config_db does matching is based on the UVM component hierarchy via a set of strings which is based on the name string arguments used during the build/create process. There is an overall top level component which gets constructed at the beginning of the UVM execution, all other components are then folded underneath this according to the testbench hierarchy.
Virtual interfaces are a SV way of being able to pass a handle to a static interface. They are a special case.
The way I recommend you pass a virtual interface to the UVM classes via the top level is as follows:
module tb;
// Interface declaration
my_if dut_port_if();
initial begin
uvm_config_db #(virtual my_if)::set(null, “uvm_test_top”, “dut_port”, dut_port_if);
run_test();
end
endmodule: tb
About the arguments in the set call:
1st argument - This is expected to be a uvm_component handle, none exist in the tb module, so this should be null
2nd argument - This is the auto-generated name of the top level component in the testbench - i.e. the test class
3rd argument - Any string you like, but it’s the one you’ll use to look up the handle
4th argument - The virtual interface handle
See:
https://verificationacademy.com/cookbook/Config/VirtInterfaceConfigDb