In reply to Phill_Ferg:
This is my debug flow, so for the time being, the DUT will always be compiled without an optimization step. I also use questas run manager, where optimization is enabled. This hopefully addresses the +acc option as well. The vopt in the run manager scripts have both these options.
Since i am passing file lists to vlog, i assumed i needed -mfcu? However i guess if i am not spreading declarations across different files i probably dont need this?
How will questa know what version of UVM to use if i don’t tell it?
I have shortened the code to be concise
library ieee;
use ieee.std_logic_1164.all;
package pkg_cpu_pcie is
type reg_fld_outT is record
R8_PROCESSING_CNTRL_REG_r : std_logic ;
R7_PROCESSING_CNTRL_REG_r : std_logic ;
R6_PROCESSING_CNTRL_REG_r : std_logic ;
R5_PROCESSING_CNTRL_REG_r : std_logic ;
R4_PROCESSING_CNTRL_REG_r : std_logic ;
R3_PROCESSING_CNTRL_REG_r : std_logic ;
R2_PROCESSING_CNTRL_REG_r : std_logic ;
R1_PROCESSING_CNTRL_REG_r : std_logic ;
FP_PROCESSING_CONFIG_REG_r : std_logic_vector(15 downto 0);
ITC_PROCESSING_CONFIG_REG_r : std_logic_vector(2 downto 0) ;
ITB_PROCESSING_CONFIG_REG_r : std_logic_vector(2 downto 0) ;
ITA_PROCESSING_CONFIG_REG_r : std_logic_vector(2 downto 0) ;
FI_FW_VERSION_REG_r : std_logic_vector(14 downto 0);
FV_FW_VERSION_REG_r : std_logic_vector(16 downto 0);
end record;
type reg_fld_inT is record
FI_FW_VERSION_REG_r_ip : std_logic_vector(14 downto 0);
FV_FW_VERSION_REG_r_ip : std_logic_vector(16 downto 0);
CIT_INTERNAL_TIME_REG_BASE_r_ip : std_logic_vector(31 downto 0);
ITL_INTERNAL_TIME_REG_4_r_ip : std_logic_vector(31 downto 0);
SC_NUC_CNTRL_REG_BASE_r_ip : std_logic ;
SB_NUC_CNTRL_REG_BASE_r_ip : std_logic ;
SA_NUC_CNTRL_REG_BASE_r_ip : std_logic ;
end record;
end package pkg_cpu_pcie;
Now for some Sv code:
My interface with the record:
interface registerHW_if(input clock, input reset);
import pkg_cpu_pcie::*;
// Control whether checks are enabled.
bit has_checks = 1 ;
// Control whether coverage is enabled.
bit has_coverage = 1 ;
// clocking block parameters
parameter setup_time = 1ns ;
parameter hold_time = 1ns ;
reg_fld_inT register_inputs ;
reg_fld_outT register_outputs ;
clocking registerHW_cb @ (posedge clock) ;
default input #setup_time output #hold_time ;
input register_outputs ;
output register_inputs ;
endclocking:registerHW_cb
endinterface : registerHW_if
And the top level where i connect the same tpes:
// register Hardware pins
.reg_fld_in (registerHW_interface.register_inputs),
.reg_fld_out (registerHW_interface.register_outputs),