Verilog inter vs intra delay

SystemVerilog
2

In reply to DVJoe:
Hi,

You can generate clock with an intra-assignment delay with some active event as shown below.


module top();
 
  reg clk;
 
  always @(clk)
     clk <= #5 ~clk;
 
  initial begin
    clk = 0;
    $monitor($time, " Monitor clk=%0d", clk);
 
    #50;
    $finish;
  end
 
endmodule // top

Putta Satish