Verilog code confusion, I do not understand this line of code

SystemVerilog
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4

In reply to lala:

Table 11-21 in the IEEE 1800-2017 SystemVerilog LRM tells you the result of the == and && operators are 1-bit expressions. And table 11-3 gives you the precedence for evaluating these operators.

 D = ( ( (A == 4'd8 ) && B ) && C )