Verilog case statment

In reply to dave_59:

Hi Dave,

I understand this now:

However my waveform tells a different story

When dll_speed_mode is toggling from 2’hx to 2’h0 i get an error in questa sim

When dll_speed_mode is 2’hx MAX_FREQ is 0 and not 400

Can you tell me what is causing this