Verify the frequency of a clock

SystemVerilog
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2

In reply to anvesh dangeti:

Hello so basically whatever you find at the right of that one is known as sequence match item instead the 1 is known as sequence expr. So basically let’s rewrite the code:

Let’s use the activate input (it can be declared as bit activate as variable inside your property.

property p_clk_hi(activate); 
      time v; 
      @(posedge clk) (activate, v=$time) |-> @(negedge clk) ($time-v)==500ns;
endproperty


ap_clk_hi: assert property(p_clk_hi(0));

This means that you could easily create a customized property using freq variable and function that would help you computing the period or semi one.
You can easily replace the (activate,fcall) as if(activate==1) then call facll. Do not call fcall is 0