In reply to ben@SystemVerilog.us:
But isn’t the verification plan a black box plan that deals with the requirements, whereas a tesplan is way to test the item, and that may include the hierarchical black boxes?
I follow what you are saying. Design requirements are free of implementation; a verification plan that covers those design line items would consequently be implementation free. Basically saying “hit these spectrum/profile of input stimulii, while making sure your checkers don’t flag any incorrect behavior”.
however, touching on my earlier example again… if the design team handed me some custom IP, and told me it had a FIFO (which I’ll treat as a buried hierarchical IP ); also, this FIFO is a critical data bottleneck, and thus is checked by SVA (aka it’s a very simple “embedded IP”, and therefore SVA is all that is required to make sure it’s working correctly). Are you saying the SVA constructs should be itemized out in the test plan, and not mentioned in the verification plan? I would expect to see something like in spreadsheet form somewhere.
Let’s say it was a complicated IP, and had it’s own verification testplan. This would perhaps fit into the test plan… and NOT the verification plan?