Verification Knowledge Exchange.
In this BLOG you will find posts from the Verification Academy's Harry Foster, Verification Horizon's Tom Fitzpatrick and Standard's Advocate Dennis Brophy and a host of other Verification Horizon Contributors.
The Verification Horizons Blog will provide an online forum for updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.
- SystemVerilog
- SystemVerilog Race Condition Challenge Responses
- Time for Another Revision of the SystemVerilog IEEE 1800 Standard
- What does importing a SystemVerilog package mean?
- Systemverilog Race Condition Challenge
- Asking better questions on the Verification Academy Forums with EDAPlayground
- Get Your Bits Together
- SystemVerilog Multidimensional Arrays
- Getting Organized with SystemVerilog Arrays
- SystemVerilog Static Methods
- SystemVerilog Classes with Static Properties
- SystemVerilog Parameterized Classes
- A Little Verilog Knowledge Goes A Long Way in Understanding How SystemVerilog Constraints Work
- Verification Methodology
- UVM
- Functional Safety
<li><strong>The Many Flavors of Equivalence Checking</strong>
<ul>
<li><a href="https://blogs.mentor.com/verificationhorizons/blog/2020/07/13/the-many-flavors-of-equivalence-checking-part-5-summary-of-the-most-popular-lec-and-slec-use-cases/" target="_blank" title=" Part 5, Summary of the Most Popular LEC and SLEC Use Cases">Part 5, Summary of the Most Popular LEC and SLEC Use Cases</a></li>
<li><a href="https://blogs.mentor.com/verificationhorizons/blog/2020/05/19/the-many-flavors-of-equivalence-checking-part-4-how-slec-brings-automated-exhaustive-formal-analysis-to-safety-mechanism-fault-analysis/" target=_blank" title="The Many Flavors of Equivalence Checking: Part 4, How SLEC Brings Automated, Exhaustive Formal Analysis to Safety Mechanism Verification">Part 4, How SLEC Brings Automated, Exhaustive Formal Analysis to Safety Mechanism Verification</a></li>
<li><a href="https://blogs.mentor.com/verificationhorizons/blog/2020/03/23/the-many-flavors-of-equivalence-checking-part-3-how-slec-brings-automated-exhaustive-formal-analysis-to-low-power-clock-gating-verification" target=_blank" title="The Many Flavors of Equivalence Checking: Part 3, How SLEC Brings Automated, Exhaustive Formal Analysis to Low Power Clock Gating Verification">Part 3, How SLEC Brings Automated, Exhaustive Formal Analysis to Low Power Clock Gating Verification</a></li>
<li><a href="https://blogs.mentor.com/verificationhorizons/blog/2019/07/11/the-many-flavors-of-equivalence-checking-part-1-synthesis-validation-with-lec-and-slec-a-k-a-the-most-popular-formal-apps-ever/" target="_blank" title="The Many Flavors of Equivalence Checking: Part 2, How SLEC Brings Automated, Exhaustive Formal Analysis to ECO/Bug Fix Verification">Part 2, How SLEC Brings Automated, Exhaustive Formal Analysis to ECO/Bug Fix Verification</a></li>
- Portable Stimulus
- Portable Stimulus: Are you Ready for a Verification Revolution
- Portable Stimulus and the Prius Model of New Technology Adoption
- Taking the First Step in Portable Stimulus Adoption
- Cats != Coverage
- It Don’t Mean a Thing … Without Methodology
- Portable Stimulus Standard – In Use Now
- Better Virtual Sequences with Portable Stimulus
- Applying Portable Stimulus at DAC
- Portable Test – Portable Intent, Portable Realization, or Both?
- Mentor Leads Portable Stimulus at DVCon US
- Developing Tests in Reverse with Portable Stimulus
- Verification Academy Live Seminar: Portable Stimulus
- Test Intent, Test Realization, and Separation of Concerns
- How to Reduce the Complexity of Formal Analysis
- Part 6 – Leveraging Data Independence and Non-Determinism
- Part 5 – Memory Abstraction
- Part 4 – Counter Abstraction
- Part 4 – Counter Abstraction
- Part 3 – Assertion Decomposition
- Part 2 – Reducing the Complexity of Your Assumptions
- Part 1 – Finding Where Formal Got Stuck and Some Initial Corrective Steps to Take