VCD Dumping issue

SystemVerilog
1

Requirement : Need to generate 2 dumps ( Vcd files ) in a single simulation and both having different time stamps for their generation
Issue : I am able to see one dump (output1.vcd) got generated but the second dump file (output2.vcd) didn’t get generated . What could be the issue here ? Please suggest .

module testbench;

  initial begin
    // Initial block 1
    $dumpfile("output1.vcd");
    $dumpvars(0, testbench); // Start dumping values to output1.vcd

    // Some simulation code
    #100; // Wait for 100 time units
    $dumpoff; // Stop dumping values to output1.vcd

    // More simulation code
  end

  initial begin
    // Initial block 2
    $dumpfile("output2.vcd");
    $dumpvars(0, testbench); // Start dumping values to output2.vcd

    // Additional simulation code
    #200; // Wait for 200 time units
    $dumpoff; // Stop dumping values to output2.vcd

    // More simulation code
  end

endmodule
2

Per the LRM, you can only have one VCD dumpfile active at a time. Your code is attempting to use two simultaneous dumpfiles, so the second one is ignored.

3

Thank you