Variables

SystemVerilog
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3

In reply to ben@SystemVerilog.us:

Thanks for your answer.
I want to ask one thing more that , you told that only dut ports are available to verification Engineer, then without knowing internal structure of dut, how I will predicts correct output?

Also , like I am verifying FIFO model, in Scoreboard I copied whole internal structure of FIFO as a reference model. Is this correct way of predicting results?

Please solve my queries!