Variable slicing of a fixed size packed array in systemverilog

In reply to dave_59:

Say i have a 32 bit array ex. :
arr = 0xAFAFAFAF

and i want a queue to be like this if size = 8
queue[0] = AF
queue[1] = AF
queue[2] = AF
queue[3] = AF
Hence queue size is 4.

But if the size =16 queue should be
queue[0] = AFAF
queue[1] = AFAF