Variable delay in SV

SystemVerilog
1

Hi,
I have seen SV code where a variable delay could be generated like #(delay * 1ns); but I am having a really hard time finding this in the standard.
Do you know whether the standard allows this or it is a vendor specific capability?

2

It depends on the context. In most places a delay is just an expression with no restrictions. But a delay expression in a clocking block must be a constant expression,

3

Hi Dave,

In the standard, I could only find the grammar attached, from which I could not deduce #(var * time_literal).
Could you kindly please point me to the relevant section of the standard?

{7C5B3C3C-1B68-4941-9CB5-0ECA929BECF4}

4

mintypmax_expression ::= // from A.8.3
    expression
  | expression : expression : expression

There is also

constant_mintypmax_expression ::=
   constant_expression
 | constant_expression : constant_expression : constant_expression