Valid args to randomize() Method

SystemVerilog
,
5

In reply to dave_59:

Thank you for the clear explanation .

I have a final question to end this post .


 // Code 3 
  class Base ;

 rand bit [1:0] a ;

 constraint aa { a == 0 ; }

endclass

class Ext1 extends Base;

 rand bit [1:0] a;

 constraint bb { a == 1 ; }

endclass

class Ext2 extends Ext1;

 rand bit [1:0] a;

 constraint cc { a == 2 ; }

// Override gparent Constraint aa
 constraint aa { Base::a == 2 ; }

// Override parent Constraint bb
 constraint bb { Ext1::a == 2 ; }

endclass

Ext2 e2;

 initial begin

  e2 = new();
  
  if ( e2.randomize() ) 
  $display("Success with %p ",e2 );  

 end

O/P is :: Success with ‘{super:’{super:'{a:'h2}, a:'h2}, a:'h2}

Class Scope resolution operator helps to unambiguously refer to correct variable even though none are static

However if I try to constraint via in-line Constraint ::


  // Code 4

  class Base ;

 rand bit [1:0] a ;

 constraint aa { a > 0 ; }

endclass

class Ext1 extends Base;

 rand bit [1:0] a;

 constraint bb { a > 1 ; }

endclass

class Ext2 extends Ext1;

 rand bit [1:0] a;

 constraint cc { a == 2 ; }


endclass

Ext2 e2;

 initial begin

  e2 = new();
  
  // TO_DO :: Below in-line Constraint throws Compilation Error !! 
  // Why does the Class Scope Resolution Operator work in Constraint Override but doesn't work within in-line Constraint
  
  if ( e2.randomize() with { Ext1::a == 2 ; Base::a == 2 ; } ) // Valid ??
  $display("Success with %p ",e2 );  

 end

**Since unrestricted Constraint block searches for variables in Class Object Scope first ,
shouldn’t this be considered a Valid Syntax ( even though these are non-static variables ) ??
**