Thanks, Warnerrs - this gave me a clue.
I added my typical reset bus transaction but that did not get rid of the reset-X during register operations.
What I did try (and it worked) was to modify the reg2bus() method in the adapter. It had always bothered me that this method controlled the r_wn, addr, and data signals but nothing else. Since reset is part of my transaction, I added tr.rst_n = '1; (reset-off) to the method and then the register transactions worked as expected.
virtual function uvm_sequence_item reg2bus (const ref uvm_reg_bus_op rw);
trans1 tr = trans1::type_id::create("tr");
//--------------------------------------------
// Set the transaction r_wn bit / addr / data
tr.r_wn = (rw.kind==UVM_WRITE) ? '0 : '1; // Write(0) / Read(1)
tr.addr = rw.addr;
tr.din = rw.data;
tr.rst_n = '1; // ADDED THIS - RESET-OFF
return(tr);
endfunction
The follow-on question, is this a proper technique? I suppose I could have added a soft constraint to the transaction code to keep reset off(??)
Is there a better way to handle the proper driving of reset, or is this what you (warnerrs) were talking about? Perhaps I am the only person who has had this problem(?)
Regards - Cliff