In reply to chr_sue:
In reply to adrianf0:
I do not know the details of your environment, but I believe it is quite common a VIP has a common package and is provided together with the VIP source code. Using this package in a system level is not forbidden.
You are right that VIP can provide extra common packages.
However, in my case, the parameters are propagated top->bottom. During compilation of VIP packages, compilation will fail, as parameters are unknown yet (they are defined at the level of testbench). Basically, I would need parametrized packages which don’t exist in SystemVerilog.