In reply to r7jindal:
I have my own view about using UVMC. SystemC does not have the capabilities SystemVerilog has. For this reason my recommendation is to use only SC methods in an UVM testbench. The best place or case is to use refernece models implemented in SC.
If you are using an UVM-Framework Generator a whole UVM Environment will be generated in a few hours. With the UVM Environment you have the full power of SV/UVM for your verifcation.
UVM Fremaework Generators ar eavailable free-of-charge like the EasierUVM Framework Genereator from Doulos (see Doulos KnowHow), UVMF from Mentor or any of the numerous Generators from other companies or freelancers. See also my Generator (www.christoph-suehnel.de).
Hope this gives you a better understanding.