UVM with base as Systemverilog vs UVM with base C++

[dave_59]

In reply to Sumeet Jain:

It’s probably more important that you follow a common methodology than which of these languages you choose. UVM was specifically created to accelerate the adoption of SystemVerilog for verification. A lot of concepts don’t map that well to other languages. I see the main purpose of UVM in other languages is when mixing other languages with UVM/SystemVerilog.